1. Field of the Invention
The present invention is related to bubble memory devices. More particularly, the present invention is related to the provision of a plurality of bubble generators connected to the serial write line. The generators are selectively activatable so as to reduce the access time for up dating or changing data in the serial loops of a block replicate bubble memory.
2. Description of the Prior Art
Prior art bubble memory devices have been generally classified in the U.S. Patent Office in U.S. Class 365, subclasses 1 to 44 (International Class G11C 11/14 to 19/08).
While prior art bubble memory devices have employed various sizes and arrangements of storage patterns, the present invention is particularly well suited for use with large capacity bubble memory chips which employ a plurality of large storage loops in which the bubble domains are stored in serial form. Each storage loop is preferably provided with a read port and a write port separated from each other by a distance of one-half of one loop time.
A block replicate bubble memory device having large storage loops is described by P. I. Bonyhard and J. L. Smith of Bell Laboratories in the IEEE Transactions on Magnetics, Volumn MAG 12, No. 6 (pp 614-617) December 1976.
This Bell Laboratories' article describes a 64,000 bit magnetic bubble chip having 131 storage loops of 523 bits each. Each loop is connected at its turn-around points or ends to a write major line and to a read major line. Even though this publication employs odd and even groups of storage bits and duplicates major read and write lines, the write major lines serve to supply a single bit of data to each of the connected loops in parallel fashion when information is written into the loops. Similarly, the read major lines serve to receive a single bit of data from each of the connected storage loops in parallel fashion when information is read out of the storage loops. The write major line is located one-half of one loop time away from the read major line, and the generator is located one-half of one loop time from the entry gate of the storage loop farthest from the generator. This reference also describes controlled pulses which are employed to generate bubbles, replicate or annihilate bubbles during write-transfer-in and read-transfer-out. The pulse amplitudes required to generator a bubble domain are shown to be approximately four times the amplitude required to transfer the domain from the storage loop or to transfer the bubble domain out of the storage loop.
According to this teaching, bubble domains may be transfered-out at the read-out ports so that these bubble domain positions in the storage loops are effectively cleared or emptied leaving the equivalent of a zero bit stored therein. In order to write into the storage loops, bubble positions must be first cleared using the read-out-annihilate logic, then the bubble positions cleared at the read-out ports are propagated to the write-in ports. In order to effectively coordinate the arrival of the newly generated bubble at the write-in ports, the buble generator is located one-half of one loop time distance from the furtherest storage loop. The bubbles being generated are representative of new data and are propagated in series fashion on the write major line until a complete serial word is in position opposite all of the read-in ports of the serial storage loops. Accordingly, the control logic assures that a cleared position in the storage loops is positioned opposite the write-in port when the word (or bit) in the write major line is ready to be transferred into the plural storage loops.
It will be recognized that the generated bubble and the annihilated bubble positions are propagated from bit position to bit position by the same rotating field. Thus, the generator must be located one-half of one storage loop bit time in distance from the first newly generated bit to arrive at the furtherest write-port connected to the write major line.
In most large scale bubble chips, the number of bits in each loop exceeds the number of loops by a factor of four or more, accordingly, a portion of the write major line serves as a delay line for delaying the bits being generated and propagated to the furtherest storage loop from the generator.
When it is desirable to change data in the storage loops, a simultaneous read-write operation is executed. Bubbles at the read-out port are destroyed and new bubble data is generated at the bubble generator and fed onto the write major line. Once the write major line is filled, the new data bubbles may be passed through the respective write-in ports to supply one new bit to each of the storage loops. This process must be repeated to generate another new bit for each of the storage loops. Thus, it will be understood that the major lines contain words and the serial storage loops contain one bit of each word. Accordingly, there is a time requirement equivalent to one-half of one loop time to enter each new bit into a storage loop. For purposes of this invention, one-half of one loop time shall be defined as the time required for the rotating field to propagate a bubble domain from a read port to a write port.
Further, one bit time is herein defined as the time required to propagate a bubble domain from one position in a storage loop, or a major line, to an adjacent bit position.
It would be desirable to be able to up-date information in the storage loops of a bubble chip faster than has been accomplished in the past. further, it would be desirable to be able to examine the data representative of a bubble domain in the storage loops before having to generate a new bubble domain for insertion in the storage loop.